Texture Detection With Feature Extraction on Embedded FPGA

dc.contributor.authorLora Rivera, Raúl
dc.contributor.authorOballe-Peinado, Óscar
dc.contributor.authorVidal-Verdú, Fernando
dc.date.accessioned2024-09-23T11:29:01Z
dc.date.available2024-09-23T11:29:01Z
dc.date.issued2023-04-25
dc.departamentoElectrónica
dc.description.abstractA feature extraction algorithm for texture detection oriented to its implementation on embedded electronics based on a field-programmable gate array (FPGA) is proposed in this article. Local preprocessing with smart tactile sensors can help to improve dexterity in artificial hands. Simplicity is the goal in order to achieve a hardware-friendly strategy that can be replicated and integrated with other circuitry. This is interesting, considering that tactile sensors are arrays and FPGAs are capable of parallel execution. The proposal was tested with a custom smart tactile sensor mounted on a Cartesian robot to explore different textures. A comparison with a common feature extraction approach based on the fast Fourier transform (FFT) computation was also made. In addition, the whole procedure is implemented on a system on chip (SoC) with the feature extraction on the embedded FPGA and a k-means classifier on an advanced RISC machine (ARM) core. The proposed algorithm obtains the spatial frequency components of the tactile signal but not their power. Therefore, some information is lost with respect to that provided by the FFT. Nevertheless, an 89.17% accuracy of the proposed algorithm is obtained versus 91.4% with the FFT when 12 different textures are considered, including complex and fabric textures. There is a noticeable saving in power and hardware resources. In addition, since the size of the feature vector is much smaller, data traffic and memory usage are much lower, and the classifier can be simpler.es_ES
dc.description.sponsorshipThis work was supported in part by the Spanish Government with a Formación de Profesorado Universitario (FPU) Grant given by the Ministerio de Ciencia, Innovacion y Universidades and in part by the European Regional Development Fund (ERDF) Program Funds under Contract PID2021-125091OB-I00.es_ES
dc.identifier.citationR. Lora-Rivera, Ó. Oballe-Peinado, and F. Vidal-Verdú, “Texture Detection With Feature Extraction on Embedded FPGA,” IEEE Sens. J., vol. 23, no. 11, pp. 12093–12104, Jun. 2023, doi: 10.1109/JSEN.2023.3268794.es_ES
dc.identifier.doi10.1109/JSEN.2023.3268794
dc.identifier.urihttps://hdl.handle.net/10630/32887
dc.language.isospaes_ES
dc.publisherInstitute of Electrical and Electronics Engineers Inc.es_ES
dc.rightsAttribution 4.0 Internacional
dc.rights.accessRightsopen accesses_ES
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/
dc.subjectDetectoreses_ES
dc.subjectElectrónicaes_ES
dc.subjectFourier, Transformaciones dees_ES
dc.subject.otherActive touches_ES
dc.subject.otherTactile sensores_ES
dc.subject.otherTexture detectiones_ES
dc.titleTexture Detection With Feature Extraction on Embedded FPGAes_ES
dc.typejournal articlees_ES
dc.type.hasVersionVoRes_ES
dspace.entity.typePublication
relation.isAuthorOfPublicationf46c97dc-f428-4b49-9d98-eaaf5ae974e2
relation.isAuthorOfPublication4d5646a9-1513-4a47-86e7-1c7d494066d8
relation.isAuthorOfPublication.latestForDiscoveryf46c97dc-f428-4b49-9d98-eaaf5ae974e2

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