Optimizing DSP Circuits by a New Family of Arithmetic Operators

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dc.centroE.T.S.I. Industriales_ES
dc.contributor.authorHormigo-Aguilar, Javier
dc.contributor.authorVillalba-Moreno, Julio
dc.date.accessioned2014-11-19T13:12:03Z
dc.date.available2014-11-19T13:12:03Z
dc.date.created2014-11-04
dc.date.issued2014-11-19
dc.departamentoArquitectura de Computadores
dc.descriptionIEEE Signal Processing Societyes_ES
dc.description.abstractA new family of arithmetic operators to optimize the implementation of circuits for digital signal processing is presented. Thanks to use of a new technique which reduces the quantification errors, the proposed operators may decrease significantly the size of the circuits required for most applications. That means a simultaneous reduction of area, delay and power consumption.es_ES
dc.description.sponsorshipUniversidad de Málaga. Campus de Excelencia Internacional Andalucía Tech.es_ES
dc.identifier.urihttp://hdl.handle.net/10630/8443
dc.language.isoenges_ES
dc.relation.eventdate2-11-2014 a 5-11-2014es_ES
dc.relation.eventplaceAsilomar Conference ground, Pacific Grove, California, USAes_ES
dc.relation.eventtitle48- Asilomar Conference on Signals, Systemas and Computerses_ES
dc.rights.accessRightsopen accesses_ES
dc.subjectAritmética computacionales_ES
dc.subject.otherComputer Arithmetices_ES
dc.subject.otherDSPes_ES
dc.subject.otherRounding to nearestes_ES
dc.subject.otherReal number representationes_ES
dc.titleOptimizing DSP Circuits by a New Family of Arithmetic Operatorses_ES
dc.typeconference outputes_ES
dspace.entity.typePublication
relation.isAuthorOfPublication236484d7-a8d7-4e3e-9023-5a01b84c9d5d
relation.isAuthorOfPublicatione84e469e-87d4-4dcc-a0bf-d73e8abb14f2
relation.isAuthorOfPublication.latestForDiscovery236484d7-a8d7-4e3e-9023-5a01b84c9d5d

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