RT Journal Article
T1 Floating Point HUB Adder for RISC-V Sargantana Processor
A1 Bandera-Burgueño, Gerardo
A1 Salamero, Javier
A1 Moreto, Miquel
A1 Villalba-Moreno, Julio
K1 Hardware
AB HUB format is an emerging technique to improve the hardware and time requirement when round to nearest isneeded. On the other hand, RISC-V is a open source ISA that an important number of companies are using intheir designs currently. In this paper we present a tailored floating point HUB adder that has been implementedin the Sargantana RISC-V processor
PB Cornell University
YR 2023
FD 2023
LK https://hdl.handle.net/10630/30192
UL https://hdl.handle.net/10630/30192
LA eng
NO G Bandera, J Salamero, M Moreto, J Villalba. Floating Point HUB Adder for RISC-V Sargantana Processor. RISC-V Summit Europe, Barcelona, 5-9th June 2023
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 21 ene 2026