RT Journal Article
T1 Large field-size elliptic curve processor for area-constrained applications
A1 Rashid, Muhammad
A1 Sonbul, Omar S.
A1 Irfan Zia, Muhammad Yousuf
A1 Kafi, Nadeem
A1 Sinky, Mohammed H.
A1 Arif, Muhammad
K1 Aritmética computacional
K1 Curvas elípticas
AB This article has proposed an efficient area-optimized elliptic curve cryptographic processor architecture over GF(2409) and GF(2571). The proposed architecture employs Lopez-Dahab projective point arithmetic operations. To do this, a hybrid Karatsuba multiplier of 4-split polynomials is proposed. The proposed multiplier uses general Karatsuba and traditional schoolbook multiplication approaches. Moreover, the multiplier resources are reused to implement the modular squares and addition chains of the Itoh-Tsujii algorithm for inverse computations. The reuse of resources reduces the overall area requirements. The implementation is performed in Verilog (HDL). The achieved results are provided on Xilinx Virtex 7 device. In addition, the performance of the proposed design is evaluated on ASIC 65 nm process technology. Consequently, a figure-of-merit is constructed to compare the FPGA and ASIC implementations. An exhaustive comparison to existing designs in the literature shows that the proposed architecture utilizes less area. Therefore, the proposed design is the right choice for area-constrained cryptographic applications.
PB MDPI
YR 2023
FD 2023
LK https://hdl.handle.net/10630/36340
UL https://hdl.handle.net/10630/36340
LA eng
NO Rashid, M.; Sonbul, O.S.; Zia, M.Y.I.; Kafi, N.; Sinky, M.H.; Arif, M. Large Field-Size Elliptic Curve Processor for Area-Constrained Applications. Appl. Sci. 2023, 13, 1240. https://doi.org/10.3390/app13031240
NO Partial funding for open access charge: Universidad de MálagaThe authors would like to thank the Deanship of Scientific Research at Umm Al-Qura University for supporting this work by Grant Code: (22UQU4320020DSR01).
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 20 ene 2026