RT Conference Proceedings
T1 Aceleración HW con FPGA de la codificación de canal mediante el interfaz PCIe y DMA.
A1 Rodríguez Cortés, Luis
A1 Entrambasaguas-Muñoz, José Tomás
A1 Martín-Vega, Francisco-Javier
A1 Aguayo-Torres, María del Carmen
K1 Sistemas de comunicaciones móviles
AB Hardware acceleration has gained renewed interestrecently due to its great potential to solve the computationalburdens associated with SW based implementation of real timecommunication systems. This approach considers SW basedimplementation of most of the communication functions dueto its fast development cycles and great flexibility comparedto HW development. However, those functions that are computationally demanding are implemented in HW to greatly reducethe computational time. Due to its iterative nature, channelencoding and decoding is related to high computational costs.This motivated us to develop a solution to this problem byoffloading the encoding function to an FPGA. To minimizecommunication time between the computer and the FPGA, thePCIe interface is used, which achieves high transfer speeds. Theresults show the encoding of the message both in the computerand in the FPGA, along with their corresponding validation andperformance metrics.
YR 2025
FD 2025-09-05
LK https://hdl.handle.net/10630/40423
UL https://hdl.handle.net/10630/40423
LA spa
NO MCIN/AEI/10.13039/501100011033
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 21 ene 2026