RT Journal Article
T1 Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform.
A1 Rodríguez-Moreno, Andrés
A1 González-Navarro, María Ángeles
A1 Asenjo-Plaza, Rafael
A1 Corbera-Peña, Francisco Javier
A1 Gran-Tejero, Rubén
A1 Suárez Gracia, Darío
A1 Núñez-Yáñez, José
K1 Computación heterogénea
K1 Arquitectura de ordenadores
AB Herogeneous computing that exploits simultaneous co-processing with different device types has been shown to be effective at both increasing performance and reducing energy consumption. In this paper, we extend a scheduling framework encapsulated in a high-level C++ template and previously developed for heterogeneous chips comprising CPU and GPU cores, to new high-performance platforms for the data center, which include a cache coherent FPGA fabric and many-core CPU resources. Our goal is to evaluate the suitability of our framework with these new FPGA-based platforms, identifying performance benefits and limitations.We target the state-of-the-art HARP processor that includes 14 high-end Xeon classes tightly coupled to a FPGA device located in the same package. We select eight benchmarks from the high-performance computing domain that have been ported and optimized for this heterogeneous platform. The results show that a dynamic and adaptive scheduler that exploits simultaneous processing among the devices can improve performance up to a factor of 8 × compared to the best alternative solutions that only use the CPU cores or the FPGA fabric. Moreover, our proposal achieves up to 15% and 37% of improvement compared to the best heterogeneous solutions found with a dynamic and static schedulers, respectively.
PB Springer
YR 2020
FD 2020
LK https://hdl.handle.net/10630/40606
UL https://hdl.handle.net/10630/40606
LA eng
NO Rodríguez, A., Navarro, A., Asenjo, R. et al. Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform. J Supercomput 76, 4645–4665 (2020)
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 19 ene 2026