RT Conference Proceedings
T1 High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS.
A1 Hormigo-Jimenez, Marco
A1 Hormigo-Aguilar, Javier
K1 Matrices lógicas programables por el usuario
K1 Algoritmos computacionales
K1 Circuitos digitales
AB Dynamic Time Warping (DTW) is a dynamic programmingalgorithm that is known to be one of the best methodsto measure the similarities between two signals, even if there arevariations in the speed of those. It is extensively used in manymachine learning algorithms, especially for pattern recognitionand classification. U nfortunately, i t h as a q uadratic complexity,which results in very high computational costs. Furthermore,its data dependency made it also very difficult t o parallelize.Special attention has been paid to computing DTW on the edge,as a way to reduce the load of communication on Internet-of-Thing applications. In this work, we propose a minimum areaimplementation of the DTW algorithm in AMD FPGAs withoptimal use of the resources. That is achieved by maximizingthe use time of the resources and taking advantage of the innerstructure of the AMD FPGAs. This architecture could be used insmall devices or as a base for a multi-core implementation withvery high-throughput.
YR 2023
FD 2023
LK https://hdl.handle.net/10630/28260
UL https://hdl.handle.net/10630/28260
LA eng
NO High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS," 2023 38th Conference on Design of Circuits and Integrated Systems (DCIS), Málaga, Spain, 2023, pp. 1-6, doi: 10.1109/DCIS58620.2023.10335963
NO MCIN/AEI/10.13039/501100011033and European Union Next Generation EU/PRTR under Project TED2021-131527B-I00; by the Fondo Europeo de Desarrollo Regional (UMA20-FEDERJA-059); and by AMD™(Xilinx™) University ProgramUniversidad de Málaga. Campus de Excelencia Internacional Andalucía Tech.
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 22 ene 2026