RT Journal Article
T1 Frequency locked loop architecture for phase noise reduction in wideband low-noise microwave oscillators.
A1 Ávila Ruiz, Juan Manuel
A1 Moreno-Pozas, Laureano
A1 Durán Valdeiglesias, Elena
A1 Moscoso Mártir, Álvaro
A1 Molina-Fernández, Íñigo
A1 De-Oliva-Rubio, José
K1 Microondas
AB A frequency locked loop (FLL) for phase noise reduction of wideband voltage controlled oscillators is proposed. The key building block of the system is a low noise (−160 dBV/Hz) and high sensitivity (22 V/GHz) delay line frequency discriminator with 5–8 GHz coverage, which makes use of a high performance multilayer hybrid. The authors derive closed-form, universal design equations for the maximum noise reduction and stability of the FLL circuitry. Application of the proposed technique to a state-of-the-art voltage controlled oscillator operating in the 5–8 GHz band yields a phase noise reduction of 8–10 dB at 100 kHz and 5 dB at 1 MHz off the carrier, which shows the results are in good agreement with the simulated results; so phase noise better than −107 dBc/Hz at 100 kHz and better than −123.5 dBc/Hz at 1 MHz is obtained.
PB Wiley
YR 2013
FD 2013
LK https://hdl.handle.net/10630/33120
UL https://hdl.handle.net/10630/33120
LA eng
NO Ávila-Ruiz, J.M., Moreno-Pozas, L., Durán-Valdeiglesias, E., Moscoso-Mártir, A., Molina-Fernández, I. and de-Oliva-Rubio, J. (2013), Frequency locked loop architecture for phase noise reduction in wideband low-noise microwave oscillators. IET Microw. Antennas Propag., 7: 869-875.
NO Política de acceso abierto tomada de: https://digital-library.theiet.org/files/Author_self-archiving_policy.pdf
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 20 ene 2026