RT Conference Proceedings
T1 Efficient Floating-Point Representation for Balanced Codes for FPGA Devices
A1 Villalba-Moreno, Julio
A1 Hormigo-Aguilar, Javier
A1 Corbera-Peña, Francisco Javier
A1 González, Mario
A1 López-Zapata, Emilio
K1 Aritmética computacional
AB We propose a floating–point representation to dealefficiently with arithmetic operations in codes with a balancednumber of additions and multiplications for FPGA devices. Thevariable shift operation is very slow in these devices. We proposea format that reduces the variable shifter penalty. It is based ona radix–64 representation such that the number of the possibleshifts is considerably reduced. Thus, the execution time of thefloating–point addition is highly optimized when it is performedin an FPGA device, which compensates for the multiplicationpenalty when a high radix is used, as experimental results haveshown. Consequently, the main problem of previous specific highradixFPGA designs (no speedup for codes with a balancednumber of multiplications and additions) is overcome with ourproposal. The inherent architecture supporting the new formatworks with greater bit precision than the corresponding singleprecision (SP) IEEE–754 standard.
YR 2013
FD 2013-10-30
LK http://hdl.handle.net/10630/6191
UL http://hdl.handle.net/10630/6191
LA eng
NO Trabajo premiado con Best paper Award
NO Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech.                  IEEE, IEEE Computer Society
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 21 ene 2026