RT Conference Proceedings
T1 FPGA acceleration of bit-true simulations for word-length optimization.
A1 Hormigo-Aguilar, Javier
A1 Caffarena, Gabriel
K1 Matemáticas computacionales
K1 Arquitectura de ordenadores
AB The end of Moore's law and the arrival of new highly demanding applications have awakened the interest in exploring different number representation formats and also combining them to implement domain-specific accelerators. Typically used in DSP applications, word-length optimization (WLO) allows finding the optimum combination of word-lengths for each signal on a circuit for a given error threshold. In the optimization process, for any word-length combination, the error has to be estimated or computed by bit-true simulation. The latter is widely used since it can be applied to any type of system. However, simulation is very time-consuming, and the WLO becomes an extremely long process. This paper proposes a methodology based on a WLO-wise hardware architecture that speeds up WLO significantly. In our approach, the target datapath is implemented on an FPGA with a “precision limiter” on each selected signal. This architecture allows performing bit-true emulation on the FPGA for any given word-length combination without reconfiguring the FPGA; just configuring the limiters, which is a much faster process.
PB IEEE
YR 2021
FD 2021
LK https://hdl.handle.net/10630/32059
UL https://hdl.handle.net/10630/32059
LA eng
NO J. Hormigo and G. Caffarena, "FPGA acceleration of bit-true simulations for word-length optimization," 2021 IEEE 28th Symposium on Computer Arithmetic (ARITH), Lyngby, Denmark, 2021, pp. 119-122, doi: 10.1109/ARITH51176.2021.00033
NO Spanish Ministry of Science, Innovation and Universities through the projects RTI2018-095324-B-I00 and PID2019-105396RBI00, and by Junta de Andalucía through P18-FR-3130Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech.
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 19 ene 2026