RT Journal Article
T1 Teaching the Cache Memory System Using a Reconfigurable Approach
A1 Quislant-del-Barrio, Ricardo
A1 Herruzo, Ezequiel
A1 Plata-González, Óscar Guillermo
A1 Benavides, Jose Ignacio
A1 Zapata, Emilio L.
K1 Arquitectura de ordenadores - Estudio y enseñanza
AB This paper presents a tool that simulates a reconfigurable cache whose parameters can be changed at runtime through a special instruction at the instruction set architecture (ISA) level. The proposed tool simulates a cache system that can be reconfigured within a variety of 298 combinations of cache capacity, number of ways or associativity, and line/block size in words (C, W, and L) without changing its architecture. The simulator was developed through a series of laboratory exercises in computer architecture. The students are introduced to the reconfigurable cache architecture while refreshing their knowledge on computer architecture issues like logic design, and register transfer level and computer system level architectures, as well as reinforcing conceptsabout memory system organization and architecture. This paper presents an overview of the reconfigurable cache and a descriptionof the simulator interface. Finally, feedback from the students provides assessment on using the simulator in the laboratory.
PB IEEE
YR 2008
FD 2008
LK https://hdl.handle.net/10630/32708
UL https://hdl.handle.net/10630/32708
LA eng
NO IEEE Transactions on Education;Vol. 51, no. 3, august 2008
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 13 abr 2026