RT Conference Proceedings
T1 Floating–Point Fused Multiply–Add under HUB Format.
A1 Hormigo-Aguilar, Javier
A1 Villalba-Moreno, Julio
A1 González-Navarro, Sonia
K1 Aritmética computacional
K1 Arquitectura de ordenadores
AB The Half-Unit-Biased (HUB) format has interesting advantages for implementing floating-point arithmetic which has been proved for the four basic arithmetic operations as well as square root. Nevertheless, although Floating-point Fused Multiply-add (FMA) operation (AxB + C) is one of the most important and complex arithmetic instructions in modern processors, FMA operation for HUB numbers has not been confronted yet. In this paper, we present a design to deal with this operation under HUB format. The key points to turn the conventional FMA architecture into a HUB unit are explained. Comparing the ASIC implementation of a HUB FMA unit with the conventional one, the former reduces the required area and power up to 38% and 35%, respectively, for single-precision. For BFloat16, the HUB FMA increases the speed a 15%, and even then, reduces the area and power by 26% and 12%, respectively.
PB IEEE
YR 2020
FD 2020-06-03
LK https://hdl.handle.net/10630/40099
UL https://hdl.handle.net/10630/40099
LA eng
NO https://conferences.ieeeauthorcenter.ieee.org/author-ethics/guidelines-and-policies/post-publication-policies/#accepted
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 20 ene 2026