RT Journal Article
T1 Fast HUB Floating-point Adder for FPGA
A1 Villalba-Moreno, Julio
A1 Hormigo-Aguilar, Javier
A1 González-Navarro, Sonia
K1 Microprocesadores
AB Several previous publications have shown the areaand delay reduction when implementing real number computationusing HUB formats for both floating-point and fixed-point.In this paper, we present a HUB floating-point adder for FPGAwhich greatly improves the speed of previous proposed HUBdesigns for these devices. Our architecture is based on the doublepath technique which reduces the execution time since eachpath works in parallel. We also deal with the implementation ofunbiased rounding in the proposed adder. Experimental resultsare presented showing the goodness of the new HUB adder forFPGA.
YR 2018
FD 2018-10-17
LK https://hdl.handle.net/10630/16620
UL https://hdl.handle.net/10630/16620
LA spa
NO TIN2016- 80920-R, JA2012 P12-TIC-1692, JA2012 P12-TIC-1470
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 3 mar 2026