RT Journal Article
T1 Throughput/Area-Efficient Accelerator of Elliptic Curve Point Multiplication over GF(2233) on FPGA
A1 Rashid, Muhammad
A1 Sonbul, Omar S.
A1 Zia, Muhammad Yousuf Irfan
A1 Arif, Muhammad
A1 Sajid, Asher
A1 Alotaibi, Saud S.
K1 Hardware - Diseño y construcción
K1 Sistemas informáticos
AB This paper presents a throughput/area-efficient hardware accelerator architecture for elliptic curve point multiplication (ECPM) computation over GF(2233). The throughput of the proposed accelerator design is optimized by reducing the total clock cycles using a bit-parallel Karatsuba modular multiplier. We employ two techniques to minimize the hardware resources: (i) a consolidated arithmetic unit where we combine a single modular adder, multiplier, and square block instead of having multiple modular operators, and (ii) an Itoh–Tsujii inversion algorithm by leveraging the existing hardware resources of the multiplier and square units for multiplicative inverse computation.An efficient finite-state-machine (FSM) controller is implemented to facilitate control functionalities. To evaluate and compare the results of the proposed accelerator architecture against state-of-the-art solutions, a figure-of-merit (FoM) metric in terms of throughput/area is defined. The implementation results after post-place-and-route simulation are reported for reconfigurable field-programmable gate array (FPGA) devices. Particular to Virtex-7 FPGA, the accelerator utilizes 3584 slices, needs 7208 clockcycles, operates on a maximum frequency of 350 MHz, computes one ECPM operation in 20.59  s, and the calculated value of FoM is 13.54. Consequently, the results and comparisons reveal that our accelerator suits applications that demand throughput and area-optimized ECPM implementations.
PB MDPI
YR 2023
FD 2023-08
LK https://hdl.handle.net/10630/29519
UL https://hdl.handle.net/10630/29519
LA eng
NO Rashid, M., Sonbul, O. S., Zia, M. Y. I., Arif, M., Sajid, A., & Alotaibi, S. S. (2023). Throughput/Area-Efficient Accelerator of Elliptic Curve point multiplication over GF(2233) on FPGA. Electronics, 12(17), 3611. https://doi.org/10.3390/electronics12173611
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 20 ene 2026