RT Conference Proceedings
T1 Energy Efficiency of Software Transactional Memory in a Heterogeneous Architecture
A1 Villegas Fernández, Emilio
A1 Villegas Fernández, Alejandro
A1 González-Navarro, María Ángeles
A1 Asenjo-Plaza, Rafael
A1 Ukidave, Yash
A1 Plata-González, Óscar Guillermo
K1 Computación heterogénea
AB Hardware vendors make an important effort creating low-power CPUs that keep battery duration and durability above acceptable levels. In order to achieve this goal and provide good performance-energy for a wide variety of applications, ARM designed the big.LITTLE architecture. This heterogeneous multi-core architecture features two different types of cores: big cores oriented to performance and little cores, slower and aimed to save energy consumption. As all the cores have access to the same memory, multi-threaded applications must resort to some mutual exclusion mechanism to coordinate the access to shared data by the concurrent threads. Transactional Memory (TM) represents an optimistic approach for shared-memory synchronization.To take full advantage of the features offered by software TM, but also benefit from the characteristics of the heterogeneous big.LITTLE architectures, our focus is to propose TM solutions that take into account the power/performance requirements of the application and what it is offered by the architecture. In order to understand the current state-of-the-art and obtain useful information for future power-aware software TM solutions, we have performed an analysis of a popular TM library running on top of an ARM big.LITTLE processor. Experiments show, in general, better scalability for the LITTLE cores for most of the applications except for one, which requires the computing performance that the big cores offer.
YR 2016
FD 2016-09-07
LK http://hdl.handle.net/10630/11969
UL http://hdl.handle.net/10630/11969
LA eng
NO Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech.
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 3 mar 2026