RT Journal Article
T1 Measuring Improvement when Using HUB Formats to Implement Floating-Point Systems under Round-to-Nearest
A1 Hormigo-Aguilar, Javier
A1 Villalba-Moreno, Julio
K1 Optimización
AB This paper analyzes the benefits of using HUBformats to implement floating-point arithmetic under round-tonearestmode from a quantitative point of view. Using HUBformats to represent numbers allows the removal of the roundinglogic of arithmetic units, including sticky-bit computation. Thisis shown for floating-point adders, multipliers, and converters.Experimental analysis demonstrates that HUB formats and thecorresponding arithmetic units maintain the same accuracy asconventional ones. On the other hand, the implementation ofthese units, based on basic architectures, shows that HUB formatssimultaneously improve area, speed, and power consumption.Specifically, based on data obtained from the synthesis, a HUBsingle-precision adder is about 14% faster but consumes 38% lessarea and 26% less power than the conventional adder. Similarly, aHUB single-precision multiplier is 17% faster, uses 22% less area,and consumes slightly less power than conventional multiplier. Atthe same speed, the adder and multiplier achieve area and powerreductions of up to 50% and 40%, respectively.
PB IEEE
SN 1063-8210
YR 2016
FD 2016
LK http://hdl.handle.net/10630/11200
UL http://hdl.handle.net/10630/11200
LA eng
NO J. Hormigo; J. Villalba, "Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol.PP, no.99, pp.1-9
NO MEC bajo TIN2013-42253-P
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 21 ene 2026