RT Journal Article
T1 Advanced Quantization Schemes to Increase Accuracy, Reduce Area, and Lower Power Consumption in FFT Architectures.
A1 Garrido, Mario
A1 Bautista, Víctor Manuel
A1 Portas, Alejandro
A1 Hormigo-Aguilar, Javier
K1 Arquitectura de ordenadores
K1 Matemáticas computacionales
AB This paper explores new advanced quantization schemes for fast Fourier transform (FFT) architectures. In previous works, FFT quantization has been treated theoretically or with the sole aim of improving accuracy. In this work, we go one step beyond by considering also the implications that quantization schemes have on the area and power consumption of the architecture. To achieve this, we have analyzed the mathematical operations carried out in FFT architectures and explored the changes that benefit all the figures of merit. By combining or alternating truncation and rounding, and using the half-unit biased (HUB) representation in the different computations of the architecture, we have achieved quantization schemes that increase accuracy, reduce area, and lower power consumption simultaneously. This win-win result improves multiple figures of merit without worsening any other, making it a valuable strategy to optimize FFT architectures.
PB IEEE
YR 2024
FD 2024
LK https://hdl.handle.net/10630/32122
UL https://hdl.handle.net/10630/32122
LA eng
NO M. Garrido, V. M. Bautista, A. Portas and J. Hormigo, "Advanced Quantization Schemes to Increase Accuracy, Reduce Area, and Lower Power Consumption in FFT Architectures," in IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2024.3421348.
NO MCIN/AEI/10.13039/501100011033 and “ERDF A Way of Making Europe” under Project PID2021-126991NA-I00, European Union NextGeneration EU/PRTR under Project TED2021-131527B-I00, Fondo Europeo de Desarrollo Regional under Grant UMA20-FEDERJA-059, and MCIN/AEI/10.13039/501100011033 and “ESF Investing in Your Future” under Grant RYC2018-025384-I
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 19 ene 2026