RT Journal Article
T1 High-radix formats for enhancing floating-point FPGA implementations
A1 Villalba-Moreno, Julio
A1 Hormigo-Aguilar, Javier
K1 Matemáticas computacionales
AB This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point support. Since variable shifter implementation (required in any FP adder) has a very high cost in FPGA, high-radix formats considerably reduce the number of possible shifts, decreasing the execution time and area highly. Although the high-radix format produces also a significant penalty in the implementation of multipliers, the experimental results show that the adder improvement overweights the multiplication penalty for most of the practical and common cases (digital filters, matrix multiplications, etc.). We also provide the designer with guidelines on selecting a suitable radix as a functionof the ratio between the number of additions and multiplications of the targeted algorithm. For applications with similar numbers of additions and multiplications, the high-radix version may be up to 26% faster and even having a wider dynamic rangeand using higher number of significant bits. Furthermore, thanks to the proposed efficient converters between the standard IEEE-754 format and our internal high-radix format, the cost of the input/output conversions in FPGA accelerators is negligible.
PB Springer
YR 2022
FD 2022-03
LK https://hdl.handle.net/10630/28905
UL https://hdl.handle.net/10630/28905
LA eng
NO Villalba, J., Hormigo, J. High-Radix Formats for Enhancing Floating-Point FPGA Implementations. Circuits Syst Signal Process 41, 1683–1703 (2022). https://doi.org/10.1007/s00034-021-01855-x
NO This research has been partially funded by the Spanish Ministry of Science, Innovation and Universities through the projects PID2019-105396RBI00 and by Junta de Andalucía through P18-FR-3130.
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 22 ene 2026