RT Conference Proceedings
T1 Pipeline template for streaming applications on heterogeneous chips
A1 Rodríguez, Andrés
A1 González-Navarro, María Ángeles
A1 Asenjo-Plaza, Rafael
A1 Corbera-Peña, Francisco Javier
A1 Vilches Reina, Antonio
A1 Garzarán, María
K1 Programación en paralelo (Informática)
AB We address the problem of providing support for executing singlestreaming applications implemented as a pipeline of stages that runon heterogeneous chips comprised of several cores and one on-chipGPU. In this paper, we mainly focus on the API that allows the userto specify the type of parallelism exploited by each pipeline stagerunning on the multicore CPU, the mapping of the pipeline stages tothe devices (GPU or CPU), and the number of active threads.  We usea real streaming application as a case of study to illustrate theexperimental results that can be obtained with this API.  With thisexample, we evaluate how the different parameter values affect theperformance and energy efficiency of a heterogenous on-chipprocessor (Exynos 5 Octa) that has three different computationalcores: a GPU, an ARM Cortex-A15 quad-core, and an ARM Cortex-A7quad-core.
YR 2015
FD 2015-09-07
LK http://hdl.handle.net/10630/10213
UL http://hdl.handle.net/10630/10213
LA eng
NO Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech. Proyecto de Excelencia de la Junta de Andalucía P11-TIC-08144.
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 4 mar 2026