RT Journal Article
T1 Speculative Barriers with Transactional Memory
A1 Pedrero-Luque, Manuel
A1 Quislant-del-Barrio, Ricardo
A1 Gutiérrez-Carrasco, Eladio Damián
A1 López-Zapata, Emilio
A1 Plata-González, Óscar Guillermo
K1 Informática
AB Transactional Memory (TM) is a synchronization model for parallel programming which provides optimistic concurrency control. Transactions can run in parallel and are only serialized in case of conflict. In this work we use hardware TM (HTM) to implement an optimistic speculative barrier (SB) to replace the lock-based solution. SBs leverage HTM support to elide barriers speculatively. When a thread reaches an SB, a new SB transaction is started, keeping the updates private to the thread, and letting the HTM system detect potential conflicts. Once the last thread reaches the corresponding SB, the speculative threads can commit their changes. The main contributions of this work are: an API for SBs implemented with HTM extensions; a procedure to check the speculation state in between barriers to enable SBs with non-transactional codes; a HTM SB-aware conflict resolution enhancement where SB transactions stall on a conflict with a standard transaction; and a set of SB use guidelines derived from our experience on using SBs in a variety of applications. We evaluated our proposals in two different architectures with a full-system simulator and an IBM Power8 server. Results show an overall performance improvement of SBs over traditional barriers.
PB IEEE
YR 2020
FD 2020-12-14
LK https://hdl.handle.net/10630/20928
UL https://hdl.handle.net/10630/20928
LA eng
NO Pedrero, M., Quislant, R., Gutierrez, E., Zapata, E. L., & Plata, O. (2020). Speculative Barriers with Transactional Memory. IEEE Transactions on Computers.
DS RIUMA. Repositorio Institucional de la Universidad de Málaga
RD 20 ene 2026