<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-06-04T06:13:20Z</responseDate><request verb="GetRecord" identifier="oai:riuma.uma.es:10630/10273" metadataPrefix="rdf">https://riuma.uma.es/rest/oai/request</request><GetRecord><record><header><identifier>oai:riuma.uma.es:10630/10273</identifier><datestamp>2026-02-03T10:53:16Z</datestamp><setSpec>com_10630_2254</setSpec><setSpec>col_10630_37953</setSpec></header><metadata><rdf:RDF xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:doc="http://www.lyncode.com/xoai" xmlns:ds="http://dspace.org/ds/elements/1.1/" xmlns:ow="http://www.ontoweb.org/ontology/1#" xmlns:rdf="http://www.openarchives.org/OAI/2.0/rdf/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/rdf/ http://www.openarchives.org/OAI/2.0/rdf.xsd">
   <ow:Publication rdf:about="oai:riuma.uma.es:10630/10273">
      <dc:title>High-Throughput FPGA Implementation of QR Decomposition</dc:title>
      <dc:creator>Muñoz, Sergio D.</dc:creator>
      <dc:creator>Hormigo-Aguilar, Javier</dc:creator>
      <dc:subject>Arquitectura de ordenadores</dc:subject>
      <dc:description>Munoz, S.D.; Hormigo, J. "High-Throughput FPGA Implementation of QR Decomposition" IEEE Transactions on in Circuits and Systems II: Express Briefs,vol.62, no.9, pp.861-865, Sept. 2015 doi: 10.1109/TCSII.2015.2435753</dc:description>
      <dc:description>This brief presents a hardware design to achieve&#xd;
high-throughput QR decomposition, using Givens Rotation Method. It utilizes a new two-dimensional systolic array architecture&#xd;
with pipelined processing elements, which are based on the COordinate Rotation DIgital Computer (CORDIC) algorithm. CORDIC computes vector rotations through shifts and additions.&#xd;
This approach allows a continuous computation of QR factorizations with simple hardware. A fixed-point FPGA architecture for 4 x 4 matrices has been optimized by balancing the number of CORDIC iterations with the final error. As a result, compared to other previous proposals for FPGA, our design achieves at least 50% more throughput, and much less resource utilization.</dc:description>
      <dc:date>2015-09-17T09:41:59Z</dc:date>
      <dc:date>2015-09-17T09:41:59Z</dc:date>
      <dc:date>2014</dc:date>
      <dc:date>2015-09-17</dc:date>
      <dc:type>journal article</dc:type>
      <dc:identifier>http://hdl.handle.net/10630/10273</dc:identifier>
      <dc:language>eng</dc:language>
      <dc:rights>open access</dc:rights>
      <dc:rights>by-nc-nd</dc:rights>
   </ow:Publication>
</rdf:RDF>
</metadata></record></GetRecord></OAI-PMH>