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                  <mods:namePart>Hormigo-Aguilar, Javier</mods:namePart>
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                  <mods:namePart>Villalba-Moreno, Julio</mods:namePart>
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               <mods:identifier type="citation">J. Hormigo; J. Villalba, "Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol.PP, no.99, pp.1-9</mods:identifier>
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               <mods:abstract>This paper analyzes the benefits of using HUB&#xd;
formats to implement floating-point arithmetic under round-tonearest&#xd;
mode from a quantitative point of view. Using HUB&#xd;
formats to represent numbers allows the removal of the rounding&#xd;
logic of arithmetic units, including sticky-bit computation. This&#xd;
is shown for floating-point adders, multipliers, and converters.&#xd;
Experimental analysis demonstrates that HUB formats and the&#xd;
corresponding arithmetic units maintain the same accuracy as&#xd;
conventional ones. On the other hand, the implementation of&#xd;
these units, based on basic architectures, shows that HUB formats&#xd;
simultaneously improve area, speed, and power consumption.&#xd;
Specifically, based on data obtained from the synthesis, a HUB&#xd;
single-precision adder is about 14% faster but consumes 38% less&#xd;
area and 26% less power than the conventional adder. Similarly, a&#xd;
HUB single-precision multiplier is 17% faster, uses 22% less area,&#xd;
and consumes slightly less power than conventional multiplier. At&#xd;
the same speed, the adder and multiplier achieve area and power&#xd;
reductions of up to 50% and 40%, respectively.</mods:abstract>
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               <mods:subject>
                  <mods:topic>Optimización</mods:topic>
               </mods:subject>
               <mods:titleInfo>
                  <mods:title>Measuring Improvement when Using HUB Formats to Implement Floating-Point Systems under Round-to-Nearest</mods:title>
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