2026-06-02T09:05:22Zhttps://riuma.uma.es/rest/oai/request

oai:riuma.uma.es:10630/119662026-02-03T11:57:31Zcom_10630_2254col_10630_37959

00925njm 22002777a 4500 dc Quislant-del-Barrio, Ricardo author Gutiérrez-Carrasco, Eladio Damián author Zapata, Emilio L. author Plata-González, Óscar Guillermo author 2016-08-24 Current industry proposals for Hardware Transactional Memory (HTM) focus on best-effort solutions (BE-HTM) where hardware limits are imposed on transactions. These designs may show a significant performance degradation due to high contention scenarios and different hardware and operating system limitations that abort transactions, e.g. cache overflows, hardware and software exceptions, etc. To deal with these events and to ensure forward progress, BE-HTM systems usually provide a software fallback path to execute a lock-based version of the code. In this paper, we propose a hardware implementation of an irrevocability mechanism as an alternative to the software fallback path to gain insight into the hardware improvements that could enhance the execution of such a fallback. Our mechanism anticipates the abort that causes the transaction serialization, and stalls other transactions in the system so that transactional work loss is mini- mized. In addition, we evaluate the main software fallback path approaches and propose the use of ticket locks that hold precise information of the number of transactions waiting to enter the fallback. Thus, the separation of transactional and fallback execution can be achieved in a precise manner. The evaluation is carried out using the Simics/GEMS simulator and the complete range of STAMP transactional suite benchmarks. We obtain significant performance benefits of around twice the speedup and an abort reduction of 50% over the software fallback path for a number of benchmarks. http://hdl.handle.net/10630/11966 http://orcid.org/0000-0001-9748-9161 Arquitectura de ordenadores Insights into the Fallback Path of Best-Effort Hardware Transactional Memory Systems