<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-06-06T04:19:30Z</responseDate><request verb="GetRecord" identifier="oai:riuma.uma.es:10630/13466" metadataPrefix="qdc">https://riuma.uma.es/rest/oai/request</request><GetRecord><record><header><identifier>oai:riuma.uma.es:10630/13466</identifier><datestamp>2026-02-03T12:18:25Z</datestamp><setSpec>com_10630_2254</setSpec><setSpec>col_10630_37959</setSpec></header><metadata><qdc:qualifieddc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:dcterms="http://purl.org/dc/terms/" xmlns:doc="http://www.lyncode.com/xoai" xmlns:qdc="http://dspace.org/qualifieddc/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://purl.org/dc/elements/1.1/ http://dublincore.org/schemas/xmls/qdc/2006/01/06/dc.xsd http://purl.org/dc/terms/ http://dublincore.org/schemas/xmls/qdc/2006/01/06/dcterms.xsd http://dspace.org/qualifieddc/ http://www.ukoln.ac.uk/metadata/dcmi/xmlschema/qualifieddc.xsd">
   <dc:title>A Physical Layer Model for G3-PLC Networks Simulation</dc:title>
   <dc:creator>Sanz, Alfredo</dc:creator>
   <dc:creator>Sancho, David</dc:creator>
   <dc:creator>Guemes, Cristian</dc:creator>
   <dc:creator>Cortés-Arrabal, José Antonio</dc:creator>
   <dc:subject>Comunicaciones</dc:subject>
   <dcterms:abstract>This work presents a model of the G3-PLC physical (PHY) layer tailored for network simulations. It allows simulating frequency selective channels with non-stationary colored noise. Collisions with other frames are modeled taking into account the length and the power of the interfering frames. Frame errors are estimated using the effective signal-to-interference-and-noise ratio mapping (ESM) function.&#xd;
The proposed PHY layer has been integrated into a distributed event-based simulator developed by Microchip. The layer 2+ stack of the simulator uses the same code that actual Microchip G3-PLC devices. Validation has been accomplished by comparing its results to a test network deployed in the laboratory. The latter consists of a coordinator and one hundred meters distributed in 5 levels. Faster-than-real-time simulations and an excellent agreement between the simulated and the measured performance indicators at the application layer have been obtained.</dcterms:abstract>
   <dcterms:dateAccepted>2017-04-19T12:58:02Z</dcterms:dateAccepted>
   <dcterms:available>2017-04-19T12:58:02Z</dcterms:available>
   <dcterms:created>2017-04-19T12:58:02Z</dcterms:created>
   <dcterms:issued>2017</dcterms:issued>
   <dc:type>conference output</dc:type>
   <dc:identifier>http://hdl.handle.net/10630/13466</dc:identifier>
   <dc:identifier>http://orcid.org/0000-0002-3914-8921</dc:identifier>
   <dc:language>eng</dc:language>
   <dc:relation>21st IEEE International Symposium on Power Line Communications and its Applications</dc:relation>
   <dc:relation>Madrid (España)</dc:relation>
   <dc:relation>03/04/2017</dc:relation>
   <dc:rights>open access</dc:rights>
   <dc:rights>by-nc-nd</dc:rights>
   <dc:publisher>IEEE</dc:publisher>
</qdc:qualifieddc>
</metadata></record></GetRecord></OAI-PMH>