2026-05-30T03:55:40Zhttps://riuma.uma.es/rest/oai/request

oai:riuma.uma.es:10630/145262026-02-03T12:05:20Zcom_10630_2254col_10630_37959

Floating Point Square Root under HUB Format Villalba-Moreno, Julio Hormigo-Aguilar, Javier Arquitectura de ordenadores Unit-Biased (HUB) is an emerging format based on shifting the representation line of the binary numbers by half unit in the last place. The HUB format is specially relevant for computers where rounding to nearest is required because it is performed simply by truncation. From a hardware point of view, the circuits implementing this representation save both area and time since rounding does not involve any carry propagation. Designs to perform the four basic operations have been proposed under HUB format recently. Nevertheless, the square root operation has not been confronted yet. In this paper we present an architecture to carry out the square root operation under HUB format for floating point numbers. The results of this work keep supporting the fact that the HUB representation involves simpler hardware than its conventional counterpart for computers requiring round-to-nearest mode. 2017-09-26T09:31:26Z 2017-09-26T09:31:26Z 2017 2017-09-26 conference output http://hdl.handle.net/10630/14526 eng The 35th IEEE International Conference on Computer Design (ICCD 2017) Newton, Boston Area, Massachusetts, USA 5/11/2017 open access by-nc-nd