2026-05-28T19:49:19Zhttps://riuma.uma.es/rest/oai/requestoai:riuma.uma.es:10630/164392026-02-03T12:36:42Zcom_10630_2254col_10630_37957
RIUMA. Repositorio Institucional de la Universidad de Málaga
advisor
González-Navarro, María Ángeles
advisor
Corbera-Peña, Francisco Javier
author
Vilches Reina, Antonio
2018-09-13T07:11:18Z
2018-09-13T07:11:18Z
2017
https://hdl.handle.net/10630/16439
During the last decade, power consumption and energy efficiency have become key aspects in processor design. Nowadays, the power consumption is the principal limitation for further scaling of chip multiprocessors design (CMPs). In general, the research community agrees that current chip multiprocessor technology trends will not scale performance without an increase of power budget. Hardware design innovations as the recent Heterogeneous Architectures and Near Threshold Computing are needed to cope with the performance-power barrier. As a result of this, there has been a shift away from chip multiprocessors to heterogeneous processor architectures. Recently, we have witnessed an explosion in the availability of this kind of architectures. Many hardware vendors have released a number of heterogeneous processors to overcome the aforementioned limitations. However, software also requires changes to allow further performance scaling on these architectures.
With the advent of heterogeneous architectures, hardware manufactures have impose the burden of explicit accelerator management on software developers. In general, programmers are used to sequential programming, but writing high-performance programs for heterogeneous architectures is a complex task. Programming for this kind of platforms requires the understanding of new hardware concepts, orchestration of different parallelism levels, the explicit management of different memory spaces and synchronisations between processing units, and finally the usage of low-level programming models such as OpenCL or CUDA. Moreover, heterogeneous architectures suffer from performance portability, as one program can exhibit unequal performance on different devices.
eng
Arquitectura de ordenadores - Tesis doctorales
Scheduling strategies for parallel patterns on heterogeneous architectures
doctoral thesis
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URL
https://riuma.uma.es/bitstreams/fd223bc0-f5b3-4756-87fb-d8d079513af6/download
File
MD5
b8a5770ae0f9821f676b399cb3647dec
11068873
application/pdf
TD_VILCHES_REINA_Antonio.pdf