2026-05-31T01:46:33Zhttps://riuma.uma.es/rest/oai/request

oai:riuma.uma.es:10630/166202026-02-03T11:25:07Zcom_10630_2254col_10630_37953

Fast HUB Floating-point Adder for FPGA Villalba-Moreno, Julio Hormigo-Aguilar, Javier González-Navarro, Sonia Microprocesadores Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point adder for FPGA which greatly improves the speed of previous proposed HUB designs for these devices. Our architecture is based on the double path technique which reduces the execution time since each path works in parallel. We also deal with the implementation of unbiased rounding in the proposed adder. Experimental results are presented showing the goodness of the new HUB adder for FPGA. 2018-10-17T08:36:03Z 2018-10-17T08:36:03Z 2018 2018-10-17 journal article https://hdl.handle.net/10630/16620 10.1109/TCSII.2018.2873194 spa IEEE Transactions on Circuits and Systems--II: Express Briefs; open access