<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-05-30T02:33:14Z</responseDate><request verb="GetRecord" identifier="oai:riuma.uma.es:10630/19259" metadataPrefix="qdc">https://riuma.uma.es/rest/oai/request</request><GetRecord><record><header><identifier>oai:riuma.uma.es:10630/19259</identifier><datestamp>2026-02-03T12:17:09Z</datestamp><setSpec>com_10630_2254</setSpec><setSpec>col_10630_37959</setSpec></header><metadata><qdc:qualifieddc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:dcterms="http://purl.org/dc/terms/" xmlns:doc="http://www.lyncode.com/xoai" xmlns:qdc="http://dspace.org/qualifieddc/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://purl.org/dc/elements/1.1/ http://dublincore.org/schemas/xmls/qdc/2006/01/06/dc.xsd http://purl.org/dc/terms/ http://dublincore.org/schemas/xmls/qdc/2006/01/06/dcterms.xsd http://dspace.org/qualifieddc/ http://www.ukoln.ac.uk/metadata/dcmi/xmlschema/qualifieddc.xsd">
   <dc:title>Accelerating time series motif discovery in the Intel Xeon Phi KNL processor.</dc:title>
   <dc:creator>Fernández-Vega, Iván</dc:creator>
   <dc:creator>Villegas Fernández, Alejandro</dc:creator>
   <dc:creator>Gutiérrez-Carrasco, Eladio Damián</dc:creator>
   <dc:creator>Plata-González, Óscar Guillermo</dc:creator>
   <dc:subject>Informática-Congresos</dc:subject>
   <dcterms:abstract>Time series analysis is an important research topic of great interest in many fields. However, the memory-bound nature of the state-of-the-art algorithms limits the execution performance in some processor architectures. We analyze the Matrix Profile algorithm from the performance viewpoint in the context of the Intel Xeon Phi Knights Landing architecture (KNL). The experimental evaluation shows a performance improvement up to 190x with respect to the sequential execution and that the use of the HBM memory improves performance in a factor up to 5x with respect to the DDR4 memory.</dcterms:abstract>
   <dcterms:dateAccepted>2020-02-11T11:59:06Z</dcterms:dateAccepted>
   <dcterms:available>2020-02-11T11:59:06Z</dcterms:available>
   <dcterms:created>2020-02-11T11:59:06Z</dcterms:created>
   <dcterms:issued>2020-02-11</dcterms:issued>
   <dc:type>conference output</dc:type>
   <dc:identifier>https://hdl.handle.net/10630/19259</dc:identifier>
   <dc:language>eng</dc:language>
   <dc:relation>HiPEAC Conference 2020</dc:relation>
   <dc:relation>Bologna (Italy)</dc:relation>
   <dc:relation>Enero 2020</dc:relation>
   <dc:rights>open access</dc:rights>
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