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oai:riuma.uma.es:10630/201242026-02-03T11:30:58Zcom_10630_2254col_10630_37953

00925njm 22002777a 4500 dc Hormigo-Aguilar, Javier author Muñoz, Sergio author 2020-10-23 High-throughput QR decomposition is a key operation in many advanced signal processing and communication applications. For some of these applications, using floating-point computation is becoming almost compulsory. However, there are scarce works in hardware implementations of floating-point QR decomposition for embedded systems. In this paper, we propose a very efficient high-throughput floating-point Givens rotation unit for QR decomposition. Moreover, the initial proposed design for conventional number formats is enhanced by using the new Half-Unit Biased format. The provided error analysis shows the effectiveness of our proposals and the trade-off of different implementation parameters. We also present FPGA implementation results and a thorough comparison between both approaches. These implementation results also reveal outstanding improvements compared to other previous similar designs in terms of area, latency, and throughput. https://hdl.handle.net/10630/20124 10.1007/s00034-020-01580-x Informática - Aplicaciones Procesado de señales Efficient floating-point givens rotation unit