2026-06-03T05:42:04Zhttps://riuma.uma.es/rest/oai/requestoai:riuma.uma.es:10630/237492026-02-03T12:22:23Zcom_10630_2254col_10630_37959
RIUMA. Repositorio Institucional de la Universidad de Málaga
author
Martín-Vega, Francisco-Javier
author
López-Martínez, Francisco Javier
author
Entrambasaguas-Muñoz, José Tomás
2022-02-06T21:31:50Z
2022-02-06T21:31:50Z
2012-09-12
https://hdl.handle.net/10630/23749
In this paper, a novel SOVA (Soft-Output Viterbi algorithm) decoder using systolic arrays to carry out the trace-back method is presented. Systolic arrays are associated with high data rates and small resource requirements, so they are especially attractive for efficient hardware implementations. The proposed architecture offers excellent performance in terms of throughput and has been used to implement a turbo decoder compliant to the 3GPP-LTE specification.
spa
Sistemas informáticos
Arquitectura HW para decodificador Two-Step SOVA con recorridos hacia atrás sistólicos
conference output
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URL
https://riuma.uma.es/bitstreams/6825cb5f-542a-484c-a418-9e296d44d409/download
File
MD5
d2700a7aa7b87137c855fd30945fe322
275831
application/pdf
DOC 3.1.7-20 URSI FPGA SOVA v2.pdf