2026-05-31T21:03:58Zhttps://riuma.uma.es/rest/oai/request

oai:riuma.uma.es:10630/241242026-02-03T10:56:13Zcom_10630_2254col_10630_37953

00925njm 22002777a 4500 dc Rodríguez-Moreno, Andrés author González-Navarro, María Ángeles author Nikov, Kris author Núñez-Yáñez, José author Gran-Tejero, Rubén author Suárez Gracia, Darío author Asenjo-Plaza, Rafael author 2022-03 The trend for heterogeneous embedded systems is the integration of accelerators and general-purpose CPU cores on the same die. In these integrated architectures, like the Zynq UltraScale+ board (CPU+FPGA) that we target in this work, hardware support for shared memory and low-overhead synchronization between the accelerator and the CPU cores make the case for exploring strategies that exploit a tight collaboration between the CPUs and the accelerator. In this paper we propose a novel lightweight scheduling strategy, FastFit, targeted to FPGA accelerators, and a new scheduler based on it, named MultiFastFit, which asynchronously tackles heterogeneous systems comprised of a variety of CPU cores and FPGA IPs. Our strategy significantly reduces the overhead to automatically compute the near-optimal chunksizes when compared to a previous state-of-the-art auto-tuned approach, which makes our approach more suitable for fine-grained applications. Additionally, our scheduler MultiFastFit has been designed to enable the efficient co-execution of work among compute devices in such a way that all the devices are busy while minimizing the load unbalance. Our approaches have been evaluated using four benchmarks carefully tuned for the low-power UltraScale+ platform. Our experiments demonstrate that the FastFit strategy always finds the near-optimal FPGA chunksize for any device configuration at a reasonable cost, even for fine-grained and irregular applications, and that heterogeneous CPU+FPGA co-executions that exploit all the compute devices are usually faster and more energy efficient than the CPU-only and FPGA-only executions. We have also compared MultiFastFit with other state-of-the-art scheduling strategies, finding that it outperforms other auto-tuned approach up to 2x and it achieves similar results to manually-tuned schedulers without requiring an offline search of the ideal CPU-FPGA partition or FPGA chunk granularity. Andrés Rodríguez, Angeles Navarro, Kris Nikov, Jose Nunez-Yanez, Rubén Gran, Darío Suárez Gracia, Rafael Asenjo, Lightweight asynchronous scheduling in heterogeneous reconfigurable systems, Journal of Systems Architecture, Volumen 124, 2022, 102398, ISSN 1383-7621, https://doi.org/10.1016/j.sysarc.2022.102398. https://hdl.handle.net/10630/24124 10.1016/j.sysarc.2022.102398 Computación heterogénea Lightweight asynchronous scheduling in heterogeneous reconfigurable systems