<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-06-02T09:05:42Z</responseDate><request verb="GetRecord" identifier="oai:riuma.uma.es:10630/24124" metadataPrefix="qdc">https://riuma.uma.es/rest/oai/request</request><GetRecord><record><header><identifier>oai:riuma.uma.es:10630/24124</identifier><datestamp>2026-02-03T10:56:13Z</datestamp><setSpec>com_10630_2254</setSpec><setSpec>col_10630_37953</setSpec></header><metadata><qdc:qualifieddc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:dcterms="http://purl.org/dc/terms/" xmlns:doc="http://www.lyncode.com/xoai" xmlns:qdc="http://dspace.org/qualifieddc/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://purl.org/dc/elements/1.1/ http://dublincore.org/schemas/xmls/qdc/2006/01/06/dc.xsd http://purl.org/dc/terms/ http://dublincore.org/schemas/xmls/qdc/2006/01/06/dcterms.xsd http://dspace.org/qualifieddc/ http://www.ukoln.ac.uk/metadata/dcmi/xmlschema/qualifieddc.xsd">
   <dc:title>Lightweight asynchronous scheduling in heterogeneous reconfigurable systems</dc:title>
   <dc:creator>Rodríguez-Moreno, Andrés</dc:creator>
   <dc:creator>González-Navarro, María Ángeles</dc:creator>
   <dc:creator>Nikov, Kris</dc:creator>
   <dc:creator>Núñez-Yáñez, José</dc:creator>
   <dc:creator>Gran-Tejero, Rubén</dc:creator>
   <dc:creator>Suárez Gracia, Darío</dc:creator>
   <dc:creator>Asenjo-Plaza, Rafael</dc:creator>
   <dc:subject>Computación heterogénea</dc:subject>
   <dcterms:abstract>The trend for heterogeneous embedded systems is the integration of accelerators and general-purpose CPU cores on the same die. In these integrated architectures, like the Zynq UltraScale+ board (CPU+FPGA) that we target in this work, hardware support for shared memory and low-overhead synchronization between the accelerator and the CPU cores make the case for exploring strategies that exploit a tight collaboration between the CPUs and the accelerator. In this paper we propose a novel lightweight scheduling strategy, FastFit, targeted to FPGA accelerators, and a new scheduler based on it, named MultiFastFit, which asynchronously tackles heterogeneous systems comprised of a variety of CPU cores and FPGA IPs. Our strategy significantly reduces the overhead to automatically compute the near-optimal chunksizes when compared to a previous state-of-the-art auto-tuned approach, which makes our approach more suitable for fine-grained applications. Additionally, our scheduler MultiFastFit has been designed to enable the efficient co-execution of work among compute devices in such a way that all the devices are busy while minimizing the load unbalance.&#xd;
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Our approaches have been evaluated using four benchmarks carefully tuned for the low-power UltraScale+ platform. Our experiments demonstrate that the FastFit strategy always finds the near-optimal FPGA chunksize for any device configuration at a reasonable cost, even for fine-grained and irregular applications, and that heterogeneous CPU+FPGA co-executions that exploit all the compute devices are usually faster and more energy efficient than the CPU-only and FPGA-only executions. We have also compared MultiFastFit with other state-of-the-art scheduling strategies, finding that it outperforms other auto-tuned approach up to 2x and it achieves similar results to manually-tuned schedulers without requiring an offline search of the ideal CPU-FPGA partition or FPGA chunk granularity.</dcterms:abstract>
   <dcterms:dateAccepted>2022-05-16T09:25:45Z</dcterms:dateAccepted>
   <dcterms:available>2022-05-16T09:25:45Z</dcterms:available>
   <dcterms:created>2022-05-16T09:25:45Z</dcterms:created>
   <dcterms:issued>2022-03</dcterms:issued>
   <dc:type>journal article</dc:type>
   <dc:identifier>Andrés Rodríguez, Angeles Navarro, Kris Nikov, Jose Nunez-Yanez, Rubén Gran, Darío Suárez Gracia, Rafael Asenjo, Lightweight asynchronous scheduling in heterogeneous reconfigurable systems, Journal of Systems Architecture, Volumen 124, 2022, 102398, ISSN 1383-7621, https://doi.org/10.1016/j.sysarc.2022.102398.</dc:identifier>
   <dc:identifier>https://hdl.handle.net/10630/24124</dc:identifier>
   <dc:identifier>10.1016/j.sysarc.2022.102398</dc:identifier>
   <dc:language>eng</dc:language>
   <dc:rights>http://creativecommons.org/licenses/by/4.0/</dc:rights>
   <dc:rights>open access</dc:rights>
   <dc:rights>Atribución 4.0 Internacional</dc:rights>
   <dc:publisher>Elsevier</dc:publisher>
</qdc:qualifieddc>
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