2026-05-29T22:33:33Zhttps://riuma.uma.es/rest/oai/requestoai:riuma.uma.es:10630/289052026-02-03T11:34:14Zcom_10630_2254col_10630_37953
RIUMA. Repositorio Institucional de la Universidad de Málaga
author
Villalba-Moreno, Julio
author
Hormigo-Aguilar, Javier
2024-01-18T13:36:39Z
2024-01-18T13:36:39Z
2022-03
Villalba, J., Hormigo, J. High-Radix Formats for Enhancing Floating-Point FPGA Implementations. Circuits Syst Signal Process 41, 1683–1703 (2022). https://doi.org/10.1007/s00034-021-01855-x
https://hdl.handle.net/10630/28905
10.1007/s00034-021-01855-x
This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point support. Since variable shifter implementation (required in any FP adder) has a very high cost in FPGA, high-radix formats considerably reduce the number of possible shifts, decreasing the execution time and area highly. Although the high-radix format produces also a significant penalty in the implementation of multipliers, the experimental results show that the adder improvement overweights the multiplication penalty for most of the practical and common cases (digital filters, matrix multiplications, etc.). We also provide the designer with guidelines on selecting a suitable radix as a function
of the ratio between the number of additions and multiplications of the targeted algorithm. For applications with similar numbers of additions and multiplications, the high-radix version may be up to 26% faster and even having a wider dynamic range
and using higher number of significant bits. Furthermore, thanks to the proposed efficient converters between the standard IEEE-754 format and our internal high-radix format, the cost of the input/output conversions in FPGA accelerators is negligible.
eng
Atribución-NoComercial-CompartirIgual 4.0 Internacional
Matemáticas computacionales
High-radix formats for enhancing floating-point FPGA implementations
journal article
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