2026-05-30T02:48:09Zhttps://riuma.uma.es/rest/oai/request

oai:riuma.uma.es:10630/301922026-02-03T10:51:57Zcom_10630_2254col_10630_37953

Floating Point HUB Adder for RISC-V Sargantana Processor Bandera-Burgueño, Gerardo Salamero, Javier Moreto, Miquel Villalba-Moreno, Julio Hardware HUB format is an emerging technique to improve the hardware and time requirement when round to nearest is needed. On the other hand, RISC-V is a open source ISA that an important number of companies are using in their designs currently. In this paper we present a tailored floating point HUB adder that has been implemented in the Sargantana RISC-V processor 2024-02-08T16:16:36Z 2024-02-08T16:16:36Z 2023 journal article G Bandera, J Salamero, M Moreto, J Villalba. Floating Point HUB Adder for RISC-V Sargantana Processor. RISC-V Summit Europe, Barcelona, 5-9th June 2023 https://hdl.handle.net/10630/30192 10.48550/arXiv.2401.09464 eng open access Cornell University