2026-06-02T10:55:54Zhttps://riuma.uma.es/rest/oai/request

oai:riuma.uma.es:10630/320592026-02-03T12:06:43Zcom_10630_2254col_10630_37959

00925njm 22002777a 4500 dc Hormigo-Aguilar, Javier author Caffarena, Gabriel author 2021 The end of Moore's law and the arrival of new highly demanding applications have awakened the interest in exploring different number representation formats and also combining them to implement domain-specific accelerators. Typically used in DSP applications, word-length optimization (WLO) allows finding the optimum combination of word-lengths for each signal on a circuit for a given error threshold. In the optimization process, for any word-length combination, the error has to be estimated or computed by bit-true simulation. The latter is widely used since it can be applied to any type of system. However, simulation is very time-consuming, and the WLO becomes an extremely long process. This paper proposes a methodology based on a WLO-wise hardware architecture that speeds up WLO significantly. In our approach, the target datapath is implemented on an FPGA with a “precision limiter” on each selected signal. This architecture allows performing bit-true emulation on the FPGA for any given word-length combination without reconfiguring the FPGA; just configuring the limiters, which is a much faster process. J. Hormigo and G. Caffarena, "FPGA acceleration of bit-true simulations for word-length optimization," 2021 IEEE 28th Symposium on Computer Arithmetic (ARITH), Lyngby, Denmark, 2021, pp. 119-122, doi: 10.1109/ARITH51176.2021.00033 https://hdl.handle.net/10630/32059 Matemáticas computacionales Arquitectura de ordenadores FPGA acceleration of bit-true simulations for word-length optimization.