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oai:riuma.uma.es:10630/363402026-02-03T10:54:39Zcom_10630_2254col_10630_37953

00925njm 22002777a 4500 dc Rashid, Muhammad author Sonbul, Omar S. author Irfan Zia, Muhammad Yousuf author Kafi, Nadeem author Sinky, Mohammed H. author Arif, Muhammad author 2023 This article has proposed an efficient area-optimized elliptic curve cryptographic processor architecture over GF(2409) and GF(2571). The proposed architecture employs Lopez-Dahab projective point arithmetic operations. To do this, a hybrid Karatsuba multiplier of 4-split polynomials is proposed. The proposed multiplier uses general Karatsuba and traditional schoolbook multiplication approaches. Moreover, the multiplier resources are reused to implement the modular squares and addition chains of the Itoh-Tsujii algorithm for inverse computations. The reuse of resources reduces the overall area requirements. The implementation is performed in Verilog (HDL). The achieved results are provided on Xilinx Virtex 7 device. In addition, the performance of the proposed design is evaluated on ASIC 65 nm process technology. Consequently, a figure-of-merit is constructed to compare the FPGA and ASIC implementations. An exhaustive comparison to existing designs in the literature shows that the proposed architecture utilizes less area. Therefore, the proposed design is the right choice for area-constrained cryptographic applications. Rashid, M.; Sonbul, O.S.; Zia, M.Y.I.; Kafi, N.; Sinky, M.H.; Arif, M. Large Field-Size Elliptic Curve Processor for Area-Constrained Applications. Appl. Sci. 2023, 13, 1240. https://doi.org/10.3390/app13031240 https://hdl.handle.net/10630/36340 10.3390/app13031240 Aritmética computacional Curvas elípticas Large field-size elliptic curve processor for area-constrained applications