2026-06-07T05:48:31Zhttps://riuma.uma.es/rest/oai/request

oai:riuma.uma.es:10630/400992026-02-03T12:16:52Zcom_10630_2254col_10630_37959

Floating–Point Fused Multiply–Add under HUB Format. Hormigo-Aguilar, Javier Villalba-Moreno, Julio González-Navarro, Sonia Aritmética computacional Arquitectura de ordenadores The Half-Unit-Biased (HUB) format has interesting advantages for implementing floating-point arithmetic which has been proved for the four basic arithmetic operations as well as square root. Nevertheless, although Floating-point Fused Multiply-add (FMA) operation (AxB + C) is one of the most important and complex arithmetic instructions in modern processors, FMA operation for HUB numbers has not been confronted yet. In this paper, we present a design to deal with this operation under HUB format. The key points to turn the conventional FMA architecture into a HUB unit are explained. Comparing the ASIC implementation of a HUB FMA unit with the conventional one, the former reduces the required area and power up to 38% and 35%, respectively, for single-precision. For BFloat16, the HUB FMA increases the speed a 15%, and even then, reduces the area and power by 26% and 12%, respectively. 2025-10-06T11:06:19Z 2025-10-06T11:06:19Z 2025-10-06T11:06:19Z 2020-06-03 conference output https://hdl.handle.net/10630/40099 10.1109/ARITH48897.2020.00010 eng 2020 IEEE 27th Symposium on Computer Arithmetic (ARITH) Portland, Oregón, USA Junio 2020 open access IEEE