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oai:riuma.uma.es:10630/406062026-02-03T11:01:54Zcom_10630_2254col_10630_37953

00925njm 22002777a 4500 dc Rodríguez-Moreno, Andrés author González-Navarro, María Ángeles author Asenjo-Plaza, Rafael author Corbera-Peña, Francisco Javier author Gran-Tejero, Rubén author Suárez Gracia, Darío author Núñez-Yáñez, José author 2020 Herogeneous computing that exploits simultaneous co-processing with different device types has been shown to be effective at both increasing performance and reducing energy consumption. In this paper, we extend a scheduling framework encapsulated in a high-level C++ template and previously developed for heterogeneous chips comprising CPU and GPU cores, to new high-performance platforms for the data center, which include a cache coherent FPGA fabric and many-core CPU resources. Our goal is to evaluate the suitability of our framework with these new FPGA-based platforms, identifying performance benefits and limitations.We target the state-of-the-art HARP processor that includes 14 high-end Xeon classes tightly coupled to a FPGA device located in the same package. We select eight benchmarks from the high-performance computing domain that have been ported and optimized for this heterogeneous platform. The results show that a dynamic and adaptive scheduler that exploits simultaneous processing among the devices can improve performance up to a factor of 8 × compared to the best alternative solutions that only use the CPU cores or the FPGA fabric. Moreover, our proposal achieves up to 15% and 37% of improvement compared to the best heterogeneous solutions found with a dynamic and static schedulers, respectively. Rodríguez, A., Navarro, A., Asenjo, R. et al. Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform. J Supercomput 76, 4645–4665 (2020) https://hdl.handle.net/10630/40606 10.1007/s11227-019-02935-1 Computación heterogénea Arquitectura de ordenadores Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform.