<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-06-01T01:23:03Z</responseDate><request verb="GetRecord" identifier="oai:riuma.uma.es:10630/40606" metadataPrefix="qdc">https://riuma.uma.es/rest/oai/request</request><GetRecord><record><header><identifier>oai:riuma.uma.es:10630/40606</identifier><datestamp>2026-02-03T11:01:54Z</datestamp><setSpec>com_10630_2254</setSpec><setSpec>col_10630_37953</setSpec></header><metadata><qdc:qualifieddc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:dcterms="http://purl.org/dc/terms/" xmlns:doc="http://www.lyncode.com/xoai" xmlns:qdc="http://dspace.org/qualifieddc/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://purl.org/dc/elements/1.1/ http://dublincore.org/schemas/xmls/qdc/2006/01/06/dc.xsd http://purl.org/dc/terms/ http://dublincore.org/schemas/xmls/qdc/2006/01/06/dcterms.xsd http://dspace.org/qualifieddc/ http://www.ukoln.ac.uk/metadata/dcmi/xmlschema/qualifieddc.xsd">
   <dc:title>Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform.</dc:title>
   <dc:creator>Rodríguez-Moreno, Andrés</dc:creator>
   <dc:creator>González-Navarro, María Ángeles</dc:creator>
   <dc:creator>Asenjo-Plaza, Rafael</dc:creator>
   <dc:creator>Corbera-Peña, Francisco Javier</dc:creator>
   <dc:creator>Gran-Tejero, Rubén</dc:creator>
   <dc:creator>Suárez Gracia, Darío</dc:creator>
   <dc:creator>Núñez-Yáñez, José</dc:creator>
   <dc:subject>Computación heterogénea</dc:subject>
   <dc:subject>Arquitectura de ordenadores</dc:subject>
   <dcterms:abstract>Herogeneous computing that exploits simultaneous co-processing with different device types has been shown to be effective at both increasing performance and reducing energy consumption. In this paper, we extend a scheduling framework encapsulated in a high-level C++ template and previously developed for heterogeneous chips comprising CPU and GPU cores, to new high-performance platforms for the data center, which include a cache coherent FPGA fabric and many-core CPU resources. Our goal is to evaluate the suitability of our framework with these new FPGA-based platforms, identifying performance benefits and limitations.We target the state-of-the-art HARP processor that includes 14 high-end Xeon classes tightly coupled to a FPGA device located in the same package. We select eight benchmarks from the high-performance computing domain that have been ported and optimized for this heterogeneous platform. The results show that a dynamic and adaptive scheduler that exploits simultaneous processing among the devices can improve performance up to a factor of 8 × compared to the best alternative solutions that only use the CPU cores or the FPGA fabric. Moreover, our proposal achieves up to 15% and 37% of improvement compared to the best heterogeneous solutions found with a dynamic and static schedulers, respectively.</dcterms:abstract>
   <dcterms:dateAccepted>2025-11-05T12:10:48Z</dcterms:dateAccepted>
   <dcterms:available>2025-11-05T12:10:48Z</dcterms:available>
   <dcterms:created>2025-11-05T12:10:48Z</dcterms:created>
   <dcterms:issued>2020</dcterms:issued>
   <dc:type>journal article</dc:type>
   <dc:identifier>Rodríguez, A., Navarro, A., Asenjo, R. et al. Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform. J Supercomput 76, 4645–4665 (2020)</dc:identifier>
   <dc:identifier>https://hdl.handle.net/10630/40606</dc:identifier>
   <dc:identifier>10.1007/s11227-019-02935-1</dc:identifier>
   <dc:language>eng</dc:language>
   <dc:rights>open access</dc:rights>
   <dc:publisher>Springer</dc:publisher>
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