2026-05-29T21:00:03Zhttps://riuma.uma.es/rest/oai/request

oai:riuma.uma.es:10630/61912026-02-03T12:04:43Zcom_10630_2254col_10630_37959

Efficient Floating-Point Representation for Balanced Codes for FPGA Devices Villalba-Moreno, Julio Hormigo-Aguilar, Javier Corbera-Peña, Francisco Javier González, Mario López-Zapata, Emilio Aritmética computacional We propose a floating–point representation to deal efficiently with arithmetic operations in codes with a balanced number of additions and multiplications for FPGA devices. The variable shift operation is very slow in these devices. We propose a format that reduces the variable shifter penalty. It is based on a radix–64 representation such that the number of the possible shifts is considerably reduced. Thus, the execution time of the floating–point addition is highly optimized when it is performed in an FPGA device, which compensates for the multiplication penalty when a high radix is used, as experimental results have shown. Consequently, the main problem of previous specific highradix FPGA designs (no speedup for codes with a balanced number of multiplications and additions) is overcome with our proposal. The inherent architecture supporting the new format works with greater bit precision than the corresponding single precision (SP) IEEE–754 standard. 2013-10-30T10:16:51Z 2013-10-30T10:16:51Z 2013-10-30T10:16:51Z 2013-10-30 conference output http://hdl.handle.net/10630/6191 eng IEEE International Conference on Computer Design ICCD2013 Asheville, NC, USA 6-10-2013 open access