2026-05-30T08:38:18Zhttps://riuma.uma.es/rest/oai/request

oai:riuma.uma.es:10630/99752026-02-03T12:13:29Zcom_10630_2254col_10630_37959

00925njm 22002777a 4500 dc Hormigo-Aguilar, Javier author Villalba-Moreno, Julio author 2015-06-29 The upcoming arrival of high dynamic range image and video applications to consumer electronics will force the utilization of floating-point numbers on them. This paper shows that introducing a slight modification on classical floating-point number systems, the implementation of those circuits can be highly improved. For a 16-bit numbers, by using the proposed format, the area and power consumption of a floating-point adder is reduced up to 70% whereas those parameters are maintained for the case of a multiplier. http://hdl.handle.net/10630/9975 https://orcid.org/0000-0002-5454-6821 Arquitectura de ordenadores Simplified Floating-Point Units for High Dynamic Range Image and Video Systems