Floating Point HUB Adder for RISC-V Sargantana Processor - Bandera-Burgueño, Gerardo; Salamero, Javier; Moreto, Miquel; Villalba-Moreno, Julio (Cornell University, 2023)
HUB format is an emerging technique to improve the hardware and time requirement when round to nearest is needed. On the other hand, RISC-V is a open source ISA that an important number of companies are using in their designs currently. In this paper we present a tailored floating point HUB adder that has been implemented in the Sargantana RISC-V processor
Keywords: Hardware; HUB format; RISC-V; ISA; FPU