• Aceleración de la computación en altas prestaciones mediante FPGA. 

      Muñoz Capo, Sergio David (UMA Editorial, 2017-07-06)
      Actualmente, cada vez es más común ver algoritmos implementados para arquitecturas heterogéneas, en las que se distinguen más de un tipo de elemento procesador. En esta tesis se quieren presentar las increíbles ventajas ...
    • Designing a Project for Learning Industry 4.0 by Applying IoT to Urban Garden 

      Hormigo-Aguilar, Javier; Rodriguez-Moreno, Andres (2019-10-11)
      The fast evolution of technologies forces teachers to trade content off for self-learning. Project-based learning (PBL) is one of the best ways to promote self-learning and simultaneously boost motivation. In this paper, ...
    • Efficient Floating-Point Representation for Balanced Codes for FPGA Devices 

      Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; Corbera, Francisco; Gonzalez, Mario; López-Zapata, Emilio (2013-10-30)
      We propose a floating–point representation to deal efficiently with arithmetic operations in codes with a balanced number of additions and multiplications for FPGA devices. The variable shift operation is very slow in ...
    • Fast HUB Floating-point Adder for FPGA 

      Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; Gonzalez-Navarro, Sonia (2018-10-17)
      Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point ...
    • Floating Point Square Root under HUB Format 

      Villalba Moreno, Julio; Hormigo-Aguilar, Javier (2017-09-26)
      Unit-Biased (HUB) is an emerging format based on shifting the representation line of the binary numbers by half unit in the last place. The HUB format is specially relevant for computers where rounding to nearest is ...
    • High-Throughput FPGA Implementation of QR Decomposition 

      Muñoz, Sergio D.; Hormigo-Aguilar, Javier (2015-09-17)
      This brief presents a hardware design to achieve high-throughput QR decomposition, using Givens Rotation Method. It utilizes a new two-dimensional systolic array architecture with pipelined processing elements, which are ...
    • Improving Fixed-Point Implementation of QR Decomposition by Rounding-to-Nearest 

      Muñoz, Sergio D.; Hormigo-Aguilar, Javier (2015-06-29)
      QR decomposition is a key operation in many current communication systems. This paper shows how to reduce the area of a fixed-point QR decomposition implementation based on Givens rotations by using a new number ...
    • Measuring Improvement when Using HUB Formats to Implement Floating-Point Systems under Round-to-Nearest 

      Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (IEEE, 2016)
      This paper analyzes the benefits of using HUB formats to implement floating-point arithmetic under round-tonearest mode from a quantitative point of view. Using HUB formats to represent numbers allows the removal of the ...
    • New formats for computing with real-numbers under round-to-nearest 

      Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (2015-09-17)
      In this paper, a new family of formats to deal with real number for applications requiring round to nearest is proposed. They are based on shifting the set of exactly represented numbers which are used in conventional ...
    • New Results on Non-normalized Floating-point Formats 

      Gonzalez-Navarro, Sonia; Hormigo-Aguilar, Javier (IEEE Computer Society, 2019)
      Compulsory normalization of the represented numbers is a key requirement of the floating-point standard. This requirement contributes to fundamental characteristics of the standard, such as taking the most of the precision ...
    • Normalizing or not normalizing? An open question for floating-point arithmetic in embedded systems 

      González-Navarro, Sonia; Hormigo-Aguilar, Javier (IEEE, 2017-07-24)
      Emerging embedded applications lack of a specific standard when they require floating-point arithmetic. In this situation they use the IEEE-754 standard or ad hoc variations of it. However, this standard was not designed ...
    • Optimizing DSP Circuits by a New Family of Arithmetic Operators 

      Hormigo-Aguilar, Javier; Villalba Moreno, Julio (2014-11-19)
      A new family of arithmetic operators to optimize the implementation of circuits for digital signal processing is presented. Thanks to use of a new technique which reduces the quantification errors, the proposed operators ...
    • Project based learning on industrial informatics: applying IoT to urban garden 

      Hormigo-Aguilar, Javier; Rodriguez-Moreno, Andres (2018-06-28)
      The fast evolution of technologies forces teachers to trade content off for self-learning. PBL is one of the best ways to promote self-learning and simultaneously boost motivation. In this paper, we present our experience ...
    • Reproducible SUmmation under HUB Format 

      Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; Jaime Rodriguez, Francisco Jose
      Floating point reproducibility is a property claimed by programmers and end users. Half-Unit-Biased (HUB) is a new representation format in which the round to nearest is carried out by truncation, preventing any ...
    • Simplified Floating-Point Units for High Dynamic Range Image and Video Systems 

      Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (2015-06-29)
      The upcoming arrival of high dynamic range image and video applications to consumer electronics will force the utilization of floating-point numbers on them. This paper shows that introducing a slight modification on ...
    • Unbiased Rounding for HUB Floating-point Addition 

      Villalba, Julio; Hormigo, Javier; González-Navarro, Sonia; Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; [et al.] (2018-06-28)
      Half-Unit-Biased (HUB) is an emerging format based on shifting the represented numbers by half Unit in the Last Place. This format simplifies two’s complement and roundto- nearest operations by preventing any carry ...