Listar por autor "Navarro, Ángeles"
Mostrando ítems 1-10 de 10
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Aceleración de Time-Series sismográficas en Python
López-Muñoz, Francisco Javier
; Grass, Thomas; Asenjo-Plaza, Rafael; Navarro, Ángeles (Miguel Angel Vega Rodríguez y Antonio J. Plaza Miguel, 2019)
Python se ha convertido en un lenguaje de programación muy popular, pero también es uno de los menos eficientes en términos de prestaciones y consumo energético. Este artículo describe el proceso que hemos seguido para ... -
Adaptive Partition Strategies for Loop Parallelism in Heterogeneous Architectures
Vilches, Antonio; Asenjo-Plaza, Rafael; Corbera-Peña, Francisco Javier; Navarro, Ángeles (2014-07-30)
This paper explores the possibility of efficiently using multicores in conjunction with multiple GPU accelerators under a parallel task programming paradigm. In particular, we address the challenge of extending a ... -
Hardware support for Local Memory Transactions on GPU Architectures
Villegas, Alejandro; Navarro, Ángeles; Asenjo-Plaza, Rafael; Plata-Gonzalez, Oscar Guillermo; Ubal, Rafael; Kaeli, David[et al.] (2015-06-26)
Graphics Processing Units (GPUs) are popular hardware accelerators for data-parallel applications, enabling the execution of thousands of threads in a Single Instruction - Multiple Thread (SIMT) fashion. However, the SIMT ... -
Hierarchical regulation of sensor data transmission for networked telerobots
Martínez-Tenor, Ángel; Gago-Benítez, Ana; Fernández-Madrigal, Juan Antonio; Cruz-Martin, Ana Maria; Asenjo-Plaza, Rafael; Navarro, Ángeles[et al.] (2014-11-18)
Networked telerobots carry sensors that send data, with stochastic transmission times, to a remote human operator, who must execute some real-time control task (e.g., navigation). In this paper we propose to regulate the ... -
Improvements in Hardware Transactional Memory for GPU Architectures
Villegas, Alejandro; Asenjo-Plaza, Rafael; Navarro, Ángeles; Plata-Gonzalez, Oscar Guillermo (2016-07-20)
In the multi-core CPU world, transactional memory (TM)has emerged as an alternative to lock-based programming for thread synchronization. Recent research proposes the use of TM in GPU architectures, where a high number of ... -
Memoria Transaccional Hardware en Memoria Local de GPU
Villegas, Alejandro; Navarro, Ángeles; Asenjo-Plaza, Rafael; Plata-Gonzalez, Oscar Guillermo (2015-09-25)
Los aceleradores gráficos (GPUs) se han convertido en procesadores de prop ́osito general muy populares para el cómputo de aplicaciones que presen- tan un gran paralelismo de datos. Su modelo de ejecución SIMT (Single ... -
On the parallelization of a three-parametric log-logistic estimation algorithm
Asenjo-Plaza, Rafael; Rodríguez, Andrés; Navarro, Ángeles; Fernández-Madrigal, Juan Antonio; Cruz-Martin, Ana Maria (2014-09-25)
Networked telerobots transmit data from its sensors to the remote controller. To provide guarantees on the time requirements of these systems it is mandatory to keep the transmission time delays below a given threshold, ... -
Patrón pipeline aplicado a arquitecturas heterogéneas big.LITTLE
Vilches, Antonio; Rodriguez-Moreno, Andres; Navarro, Ángeles; Corbera-Peña, Francisco Javier; Asenjo-Plaza, Rafael (2015-09-25)
En este trabajo, proponemos una solución para permitir la ejecución de aplicaciones de tipo streaming, que constan de una serie de etapas, sobre arquitecturas heterogéneas con un multicore y una GPU integrada. Para ello, ... -
Pipeline template for streaming applications on heterogeneous chips
Rodríguez, Andrés; Navarro, Ángeles; Asenjo-Plaza, Rafael; Corbera-Peña, Francisco Javier; Vilches, Antonio; Garzarán, María[et al.] (2015-09-07)
We address the problem of providing support for executing single streaming applications implemented as a pipeline of stages that run on heterogeneous chips comprised of several cores and one on-chip GPU. In this paper, ... -
Reducing overheads of dynamic scheduling on heterogeneous chips
Corbera-Peña, Francisco Javier; Rodríguez, Andrés; Asenjo-Plaza, Rafael; Navarro, Ángeles; Vilches, Antonio; Garzarán, María[et al.] (arXiv.org (Cornell University Library), 2015-01-19)
In recent processor development, we have witnessed the integration of GPU and CPUs into a single chip. The result of this integration is a reduction of the data communication overheads. This enables an efficient collaboration ...