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dc.contributor.authorMuñoz, Sergio D.
dc.contributor.authorHormigo-Aguilar, Javier 
dc.date.accessioned2015-09-17T09:41:59Z
dc.date.available2015-09-17T09:41:59Z
dc.date.created2014
dc.date.issued2015-09-17
dc.identifier.urihttp://hdl.handle.net/10630/10273
dc.descriptionMunoz, S.D.; Hormigo, J. "High-Throughput FPGA Implementation of QR Decomposition" IEEE Transactions on in Circuits and Systems II: Express Briefs,vol.62, no.9, pp.861-865, Sept. 2015 doi: 10.1109/TCSII.2015.2435753es_ES
dc.description.abstractThis brief presents a hardware design to achieve high-throughput QR decomposition, using Givens Rotation Method. It utilizes a new two-dimensional systolic array architecture with pipelined processing elements, which are based on the COordinate Rotation DIgital Computer (CORDIC) algorithm. CORDIC computes vector rotations through shifts and additions. This approach allows a continuous computation of QR factorizations with simple hardware. A fixed-point FPGA architecture for 4 x 4 matrices has been optimized by balancing the number of CORDIC iterations with the final error. As a result, compared to other previous proposals for FPGA, our design achieves at least 50% more throughput, and much less resource utilization.es_ES
dc.description.sponsorshipMinistry of Education and Science of Spain and Junta of Andalucia under contracts TIN2013-42253-P and P07-TIC-02630, respectively.es_ES
dc.language.isoenges_ES
dc.rightsinfo:eu-repo/semantics/openAccesses_ES
dc.subjectArquitectura de ordenadoreses_ES
dc.subject.otherQR Decompositiones_ES
dc.subject.otherSystolic arrayes_ES
dc.subject.otherPipelinedes_ES
dc.subject.otherFPGAes_ES
dc.subject.otherHigh-throughputes_ES
dc.subject.otherCORDICes_ES
dc.titleHigh-Throughput FPGA Implementation of QR Decompositiones_ES
dc.typeinfo:eu-repo/semantics/preprintes_ES
dc.centroE.T.S.I. Informáticaes_ES
dc.cclicenseby-nc-ndes_ES


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