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Digit recurence division under HUB format
dc.contributor.author | Villalba-Moreno, Julio | |
dc.date.accessioned | 2016-07-21T10:23:59Z | |
dc.date.available | 2016-07-21T10:23:59Z | |
dc.date.created | 2016 | |
dc.date.issued | 2016-07-21 | |
dc.identifier.uri | http://hdl.handle.net/10630/11872 | |
dc.description.abstract | Half-Unit-Biased format is based on shifting the representation line of the binary numbers by half Unit in the Last Place. The main feature of this format is that the round to nearest is carried out by a simple truncation, preventing any carry propagation and saving time and area. Algorithms and architectures have been defined for addition/substraction and multiplication operations under this format. Nevertheless, the division operation has not been confronted yet. In this paper we deal with the floating-point division under HUB format, studying the architecture for the digit recurrence method, including the on-the-fly conversion of the signed digit quotient. | es_ES |
dc.description.sponsorship | Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech. | es_ES |
dc.language.iso | eng | es_ES |
dc.rights | info:eu-repo/semantics/openAccess | es_ES |
dc.subject | Aritmética computacional | es_ES |
dc.subject.other | Digit recurrence division | es_ES |
dc.subject.other | HUB | es_ES |
dc.title | Digit recurence division under HUB format | es_ES |
dc.type | info:eu-repo/semantics/conferenceObject | es_ES |
dc.centro | E.T.S.I. Industrial | es_ES |
dc.relation.eventtitle | 23rd IEEE Symposium on Computer Arithmetic | es_ES |
dc.relation.eventplace | Silicon Valley, Califoria USA | es_ES |
dc.relation.eventdate | 10-07-2016 | es_ES |
dc.cclicense | by-nc-nd | es_ES |