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dc.contributor.authorVillegas, Emilio
dc.contributor.authorVillegas, Alejandro
dc.contributor.authorNavarro, Angeles
dc.contributor.authorAsenjo-Plaza, Rafael 
dc.contributor.authorUkidave, Yash
dc.contributor.authorPlata-Gonzalez, Oscar Guillermo 
dc.date.accessioned2016-09-07T12:19:20Z
dc.date.available2016-09-07T12:19:20Z
dc.date.created2016
dc.date.issued2016-09-07
dc.identifier.urihttp://hdl.handle.net/10630/11969
dc.description.abstractHardware vendors make an important effort creating low-power CPUs that keep battery duration and durability above acceptable levels. In order to achieve this goal and provide good performance-energy for a wide variety of applications, ARM designed the big.LITTLE architecture. This heterogeneous multi-core architecture features two different types of cores: big cores oriented to performance and little cores, slower and aimed to save energy consumption. As all the cores have access to the same memory, multi-threaded applications must resort to some mutual exclusion mechanism to coordinate the access to shared data by the concurrent threads. Transactional Memory (TM) represents an optimistic approach for shared-memory synchronization. To take full advantage of the features offered by software TM, but also benefit from the characteristics of the heterogeneous big.LITTLE architectures, our focus is to propose TM solutions that take into account the power/performance requirements of the application and what it is offered by the architecture. In order to understand the current state-of-the-art and obtain useful information for future power-aware software TM solutions, we have performed an analysis of a popular TM library running on top of an ARM big.LITTLE processor. Experiments show, in general, better scalability for the LITTLE cores for most of the applications except for one, which requires the computing performance that the big cores offer.es_ES
dc.description.sponsorshipUniversidad de Málaga. Campus de Excelencia Internacional Andalucía Tech.es_ES
dc.language.isoenges_ES
dc.rightsinfo:eu-repo/semantics/openAccesses_ES
dc.subjectComputación heterogéneaes_ES
dc.subject.otherTransactional Memoryes_ES
dc.subject.otherHeterogeneous Architecturees_ES
dc.titleEnergy Efficiency of Software Transactional Memory in a Heterogeneous Architecturees_ES
dc.typeinfo:eu-repo/semantics/preprintes_ES
dc.centroE.T.S.I. Informáticaes_ES
dc.relation.eventtitle8th Workshop on the Theory of Transactional Memory (WTTM 2016)es_ES
dc.relation.eventplaceChicago, Illinois, USAes_ES
dc.relation.eventdate25 de Julio de 2016es_ES
dc.cclicenseby-nc-ndes_ES


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