Unit-Biased (HUB) is an emerging format based on
shifting the representation line of the binary numbers by half
unit in the last place. The HUB format is specially relevant
for computers where rounding to nearest is required because
it is performed simply by truncation. From a hardware point
of view, the circuits implementing this representation save both
area and time since rounding does not involve any carry propagation.
Designs to perform the four basic operations have been
proposed under HUB format recently. Nevertheless, the square
root operation has not been confronted yet. In this paper we
present an architecture to carry out the square root operation
under HUB format for floating point numbers. The results of
this work keep supporting the fact that the HUB representation
involves simpler hardware than its conventional counterpart for
computers requiring round-to-nearest mode.
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