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dc.contributor.authorPedrero Luque, Manuel
dc.contributor.authorQuislant, Ricardo
dc.contributor.authorGutierrez-Carrasco, Eladio Damian 
dc.contributor.authorLópez-Zapata, Emilio 
dc.contributor.authorPlata-Gonzalez, Oscar Guillermo 
dc.date.accessioned2021-02-03T11:55:56Z
dc.date.available2021-02-03T11:55:56Z
dc.date.issued2020-12-14
dc.identifier.citationPedrero, M., Quislant, R., Gutierrez, E., Zapata, E. L., & Plata, O. (2020). Speculative Barriers with Transactional Memory. IEEE Transactions on Computers.es_ES
dc.identifier.urihttps://hdl.handle.net/10630/20928
dc.description.abstractTransactional Memory (TM) is a synchronization model for parallel programming which provides optimistic concurrency control. Transactions can run in parallel and are only serialized in case of conflict. In this work we use hardware TM (HTM) to implement an optimistic speculative barrier (SB) to replace the lock-based solution. SBs leverage HTM support to elide barriers speculatively. When a thread reaches an SB, a new SB transaction is started, keeping the updates private to the thread, and letting the HTM system detect potential conflicts. Once the last thread reaches the corresponding SB, the speculative threads can commit their changes. The main contributions of this work are: an API for SBs implemented with HTM extensions; a procedure to check the speculation state in between barriers to enable SBs with non-transactional codes; a HTM SB-aware conflict resolution enhancement where SB transactions stall on a conflict with a standard transaction; and a set of SB use guidelines derived from our experience on using SBs in a variety of applications. We evaluated our proposals in two different architectures with a full-system simulator and an IBM Power8 server. Results show an overall performance improvement of SBs over traditional barriers.es_ES
dc.language.isoenges_ES
dc.publisherIEEEes_ES
dc.rightsinfo:eu-repo/semantics/openAccesses_ES
dc.subjectInformáticaes_ES
dc.subject.otherSpeculative Barrierses_ES
dc.subject.otherHardware Transactional Memoryes_ES
dc.subject.otherShared-Memory Parallelismes_ES
dc.subject.otherIBM Power8es_ES
dc.subject.otherGEMSes_ES
dc.titleSpeculative Barriers with Transactional Memoryes_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.centroE.T.S.I. Informáticaes_ES
dc.identifier.doihttps://doi.org/10.1109/TC.2020.3044234


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