Envíos recientes

  • Designing a Project for Learning Industry 4.0 by Applying IoT to Urban Garden 

    Hormigo-Aguilar, Javier; Rodriguez-Moreno, Andres (2019-10-11)
    The fast evolution of technologies forces teachers to trade content off for self-learning. Project-based learning (PBL) is one of the best ways to promote self-learning and simultaneously boost motivation. In this paper, ...
  • New Results on Non-normalized Floating-point Formats 

    Gonzalez-Navarro, Sonia; Hormigo-Aguilar, Javier (IEEE Computer Society, 2019)
    Compulsory normalization of the represented numbers is a key requirement of the floating-point standard. This requirement contributes to fundamental characteristics of the standard, such as taking the most of the precision ...
  • ReduxSTM: Optimizing STM designs for Irregular Applications 

    Pedrero, Manuel; Gutierrez, Eladio; Romero-Montiel, Sergio; Plata, Oscar (2018-11-15)
  • Mejorando el rendimiento de la memoria transaccional para aplicaciones irregulares 

    Pedrero, Manuel; Gutiérrez, Eladio; Romero-Montiel, Sergio; Plata, Oscar (2018-11-15)
    La Memoria Transaccional (TM) ofrece un modelo de ejecución concurrente optimista en arquitecturas multinúcleo, permitiendo a los programadores extraer paralelismo cuando la información de las dependencias de datos no está ...
  • A Comparative Analysis of STM Approaches to Reduction Operations in Irregular Applications 

    Pedrero, Manuel; Gutierrez-Carrasco, Eladio Damian; Romero-Montiel, Sergio; Plata-Gonzalez, Oscar Guillermo
    As a recently consolidated paradigm for optimistic concurrency in modern multicore architectures, Transactional Memory (TM) can help to the exploitation of parallelism in irregular applications when data dependence ...
  • Fast HUB Floating-point Adder for FPGA 

    Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; Gonzalez-Navarro, Sonia (2018-10-17)
    Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point ...
  • Unbiased Rounding for HUB Floating-point Addition 

    Villalba, Julio; Hormigo, Javier; González-Navarro, Sonia; Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; [et al.] (2018-06-28)
    Half-Unit-Biased (HUB) is an emerging format based on shifting the represented numbers by half Unit in the Last Place. This format simplifies two’s complement and roundto- nearest operations by preventing any carry ...
  • Inventory control for a non-stationary demand perishable product: comparing policies and solution methods 

    Hendrix, Eligius Maria Theodorus; Pauls-Worm, Karin G.J (2018-03-02)
    This paper summarizes our findings with respect to order policies for an inventory control problem for a perishable product with a maximum fixed shelf life in a periodic review system, where chance constraints play a role. ...
  • Measuring Improvement when Using HUB Formats to Implement Floating-Point Systems under Round-to-Nearest 

    Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (IEEE, 2016)
    This paper analyzes the benefits of using HUB formats to implement floating-point arithmetic under round-tonearest mode from a quantitative point of view. Using HUB formats to represent numbers allows the removal of the ...
  • High-Throughput FPGA Implementation of QR Decomposition 

    Muñoz, Sergio D.; Hormigo-Aguilar, Javier (2015-09-17)
    This brief presents a hardware design to achieve high-throughput QR decomposition, using Givens Rotation Method. It utilizes a new two-dimensional systolic array architecture with pipelined processing elements, which are ...
  • New formats for computing with real-numbers under round-to-nearest 

    Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (2015-09-17)
    In this paper, a new family of formats to deal with real number for applications requiring round to nearest is proposed. They are based on shifting the set of exactly represented numbers which are used in conventional ...